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Technical Paper: Void Size Process Control During Die Attach of Large Area HIGH POWER Semiconductor Devices

Void Size Process Control During Die Attach of Large Area HIGH POWER Semiconductor Devices

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Abstract: To realize the full potential of increased power densities from GaAs and GaN devices, a high yielding void free manufacturing process was developed to limit void sizes to less than 0.15mm during eutectic soldering. Voiding between die and thermal spreader can significantly limit thermal heat transfer. GaAs die can handle power densities of 1.0 watt / mm while new GaN devices push this power density to 5.0 watts / mm or greater. Traditional assembly methods for attaching large area GaAs or GaN die to thermal spreaders using Au-20Sn preforms are typically poor yielding due to significant voiding under power FETs and bond pads. Thermal simulations show that voiding greater than 0.15mm under power FET’s can seriously reduce performance or in some cases cause catastrophic device failure. Without void size process control, assembly yields are significantly compromised. Void control can be significantly improved when using vacuum reflow equipment and a technique to reduce chamber pressure after the solder has transitioned from solid to liquid. Void size expansion is inhibited by a Void Expansion Slip (VES) factor, creating smaller voids and allows large compression ratios at the completion of the solder process. Adding this technique to a vacuum reflow process will produce void free solder yields greater than 98% on very large die.


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