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Quality Systems Certifications and Compliance Processes

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Reliability Analysis and Failure Analysis

Criteria Labs was established to provide Semiconductor Manufacturing Services for the defense, aerospace, medical (including life support), military, communications, automotive and computer markets. Criteria Labs is equipped to assemble and test devices used in satellites, space probes, military and commercial aircraft, ground and naval systems and implanted medical applications. In addition to assembly, test, destructive physical analysis (DPA) and device qualifications, Criteria Labs also provides complete electronic package assembly for HYBRIDS, Chip On Board, ceramic packages and smart cards.  Criteria Labs provides a complete solution of semiconductor backend manufacturing services to our customers, including front-end engineering testing, wafer probing, final testing of logic and mixed signal semiconductors. Our testing services employ technology and expertise that are among the most advanced in the semiconductor industry.

Criteria Labs has extensive microelectronic Failure Analysis process capabilities. Our engineers and analysts can evaluate your integrated circuits that may have failed during design, manufacture, qualification or service to locate and help identify the problem.

Identifying the problem or failure may require up to three (3) levels of effort and are defined as Level I, II or III.

Level I Analysis

The majority of microelectronic devices can be detected during the "Level I" analysis. The initial inspection employs the following techniques to verify packaging integrity and microscopically inspect for damage.

Level II Analysis

Level II analysis is performed upon completion of the Level I analysis when no defect was found after de-capsulation and optical or microscopic inspection. Light emission microscopy (LEM) and Liquid Crystal processes are then used to detect and locate defects.

Level III Analysis

Level III analysis is preformed upon completion of the Level II analysis and involves chemical de-layering and/or precision cross-sectioning of an IC indication site. The object is to view the indication relative to its location within the IC. Both optical and SEM inspection are employed to document the failing sites. Results of the analysis are documented with the Level I and Level II results.

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