ESD & Latch Up
Criteria Labs is a turnkey test facility for the characterization of Electro Static Discharge (ESD) and latch-up in semiconductor components. Characterization of ESD and latch-up for immunity in integrated circuits is required by industry standards, including the Mil-Std 883, the Electronic Industries Association (EIA/JEDEC), and the Automotive Electronics Council (AEC). Criteria Labs is dedicated to providing our customers with consistent, accurate testing with quality test reporting. In the event of ESD or latch-up failure, Criteria Labs analytical services staff are on-site and can quickly determine the root cause, significantly improving problem resolution cycle times.
Technical Explanation of ESD and Latch-up
Electro Static Discharge (ESD) can severely damage or destroy ICs, and specified levels of ESD protection must be demonstrated as part of most product qualifications. Criteria Labs tests devices to any commercial or military ESD standard and performs curve tracing before and after testing to check for any device changes. Criteria Labs can also identify weak points in a functioning ESD design, enabling future designs to be improved.
HBM (Human Body Model) & MM (Machine Model)
The objective is to provide reliable, repeatable HBM & MM ESD test results so that accurate classifications can be performed and microcircuits can be classified according to their susceptibility to damage or degradation by exposure to a defined electrostatic Human Body Model (HBM) & Machine Model (MM) discharge (ESD). An ESD event can destroy an IC in a number of ways, resulting in one or more of these attributes: junction leakage, short, or burn-out; dielectric rupture; resistor-metal interface rupture; resistor/metal fusing; and die surface charging.
Field-Induced Charged Device Model (CDM)
CDM testing is used to classify integrated circuits according to their triboelectric susceptibility. The charged-device-model simulates charging/discharging events that occur in production equipment and processes. Potential for CDM ESD events occurs whenever there is charge buildup and this charge rapidly discharged through a pin of the semiconductor device. Certain materials become electrically charged after coming into contact with another, different, material. The polarity and strength of the charges produced differ according to material and surface smoothness. One of many examples is a device sliding down a shipping tube hitting a metal surface. CDM ESD events not only reduce assembly yields but can also produce device damage that goes undetected by factory test and later is the cause of a latent failure.
Latch-up/Electrical Overstress (EOS)
Latch-up characteristics are extremely important in determining product reliability. This test is applicable to NMOS, CMOS, bipolar, all variations and combinations of these technologies. Latch-up is the creation of a disruptive low-impedance current path between power supply and ground, triggered by a parasitic four-layer bipolar structure in CMOS devices.
Capabilities
- Characterize all pins, establish ESD sensitivities and failure threshold
- ESD Testing per JEDEC, ESDA, Mil-Std-883 and AEC
- Testing available: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM)
- Test and characterize all package types
- Die ESD and Latch-up characterization available. Our packaging lab will assemble die into a standard dip package then test
- Automated Latch-up Testing: Static, Dynamic and Transient
- Testing available: CMOS / EIA / JEDEC No. 17 & 78; custom; elevated temperature to 160C
- Testing up to 512 pins